The present technology relates to a semiconductor device such as a solid-state imaging device or the like formed by laminating wafers, a method for manufacturing the semiconductor device, a method for laminating semiconductor wafers, and an electronic device including the solid-state imaging device.
In related art, a process of manufacturing a semiconductor device typified by a solid-state imaging device or the like includes a process of laminating two different wafers. For example, in a case of a backside illumination type solid-state imaging device described in Japanese Patent Laid-Open No. 2007-88450, there is a process of laminating a wafer having a pixel region and a peripheral circuit region formed therein to a supporting substrate. In addition, in a case of a solid-state imaging device described in Japanese Patent Laid-Open No. 2010-245506, there is a process of bonding a wafer having a pixel region formed therein to a wafer having a logic circuit formed therein such that circuit surfaces are in contact with each other.
For example, when two wafers are bonded to each other by using a plasma bonding technique, a silanol group (Si—OH group) is formed by applying plasma irradiation to a SiO2 film formed on the bonding surfaces of the wafers. Next, the laminating surfaces of the wafers are opposed to each other, and bonded to each other by a Van der Waals force by pressing a part of the wafers. Thereafter, in order to further enhance adhesion at a bonding interface, control at a molecular level in applying 400° C./60-min heat treatment and effecting dehydration condensation reaction of the silanol groups with each other, for example, is necessary for the laminating surfaces of the wafers. Thus, when the laminating surfaces of the wafers have projections and depressions, bonding at a molecular level cannot be performed.
In addition, in lamination using an adhesive, when an adhesive having high viscosity and high hardness is used, and the laminating surfaces of the wafers have projections and depressions, the adhesive does not enter spaces formed by the projections and the depressions, so that adhesion between the laminated wafers cannot be maintained.
Thus, in a case where there is a process of laminating wafers to each other, the flatness of the laminating surfaces of the wafers is very important, and bonding cannot be performed when the laminating surfaces have a local level difference caused by a wiring pattern or the like. A method for manufacturing a semiconductor device in the past which semiconductor device is formed by laminating two wafers to each other and which has wiring layers in the vicinity of the laminating surfaces of the wafers will be described with reference to FIGS. 12A to 12G.
FIGS. 12A to 12G are process diagrams showing a method for manufacturing a semiconductor device in the past. FIGS. 12A to 12G show a section of a region including a boundary part between a peripheral region 120 of a semiconductor wafer 113 and an inside region 121 of the semiconductor wafer 113 in which inside region transistors and the like forming a circuit are formed. As shown in FIG. 12A, a plurality of MOS transistors Tr composed of source/drain regions 112 and a gate electrode 103 are formed in a state of being isolated from each other by element isolation regions 114 in the inside region 121 forming a chip section on the surface side of the wafer 113.
First, a first layer of interlayer insulating film 104 is formed on the semiconductor wafer 113 made of silicon, and wiring grooves 105 are formed in a predetermined pattern in the upper surface of the interlayer insulating film 104. Thereafter, a wiring material 106 made of Cu is formed on the entire surface of the interlayer insulating film 104 including the wiring grooves 105. Then, after the wiring material is formed, a first layer of wiring 107 is formed by removing the wiring material on the surface of the interlayer insulating film 104 such that the wiring material is left only within the wiring grooves 105.
At this time, in order to prevent exposure of Cu, all of the wiring material in a certain region from an edge of the wafer is locally removed from the peripheral region 120 of the semiconductor wafer 113 by a method referred to as Cu EBR (Edge Bead Removal). The EBR process can remove the wiring material in the peripheral region 120 as shown in FIG. 12B by discharging a solvent from a dedicated discharge nozzle to the peripheral region 120 of the semiconductor wafer 113. As a result of the wiring material in the peripheral region 120 being thus removed, nothing is filled into the wiring grooves 105 formed in the peripheral region 120, and thus empty grooves are formed.
Thereafter, an interlayer insulating film 104 is formed on the wiring 107. Then, in the peripheral region 120, the wiring grooves (hereinafter empty grooves 105) in which the wiring 107 is not formed remain, and thus the interlayer insulating film 104 is absorbed by the empty grooves. As a result, as shown in FIG. 12C, the surface of the interlayer insulating film 104 has a level difference at a boundary between the inside region 121 and the peripheral region 120. Empty grooves 105 are also formed in the peripheral region 120 when a second layer of wiring 109 is formed. Thereafter, as shown in FIG. 12D, further forming an interlayer insulating film 104 and a third layer of wiring 110 increasingly enlarges the level difference of the surface of the wiring layer which level difference is formed at the boundary between the inside region 121 and the peripheral region 120.
Thus, in the process of forming the wiring layer in the past, empty grooves 105 are formed on the periphery of the wafer each time wiring is formed. Thus, as a result, regions from which the wiring is removed in the peripheral region 120 of the semiconductor wafer 113 have a small film thickness as compared with the inside region 121 in which the wiring is formed, and a large level difference is formed at the boundary between the inside region 121 and the peripheral region 120. For example, when a wiring layer having four layers of wiring is formed, there is a large level difference of 800 nm to 1000 nm between the central part and the peripheral region of the semiconductor wafer. When this surface is used as a laminating surface, lamination cannot be performed in the peripheral region.
In the past, it has been a common practice to form a P—SiO2 (plasma silicon oxide) film 111 having such a thickness as to fill in the level difference on the wiring layer by using a CVD (Chemical Vapor Deposition) method, as shown in FIG. 12E, and planarize the surface of the P—SiO2 film 111 by polishing the surface of the P—SiO2 film 111 by using a CMP (Chemical Mechanical Polishing) method, as shown in FIG. 12F. However, the film formed by the CVD method is formed along the shape of the surface. Thus, even when the film is formed with such a thickness as to fill in the level difference, the film is formed in a state of conforming to the level difference, so that the level difference is not eliminated. Further, the peripheral (edge) part of the wafer may be polished more because of an edge over-polishing profile specific to CMP. Then, as shown in FIG. 12G, when two semiconductor wafers 113 are laminated to each other with the wiring layers of the semiconductor wafers 113 as laminating surfaces, the semiconductor wafers 113 cannot be laminated to each other in the peripheral regions 120 of the semiconductor wafers 113 due to an effect of global level differences at the surfaces of the wafers. Therefore a bonding defect occurs.
FIGS. 12A to 12G represent an example in which wiring layers having a level difference on the periphery are bonded to each other. However, even in a case where one wafer is flat, a bonding defect occurs as in FIG. 12G when the surface of the wiring layer formed in the other wafer has a level difference. As shown in FIG. 12G, when a bonding defect occurs on the peripheries of the wafers, strength at the bonding surfaces cannot be maintained. Then, defects such as film peeling, chipping, and the like may occur in a polishing process after lamination and a process of dividing the wafers into each chip. Therefore reliability cannot be maintained.
In addition, while the above description mentions the local removal of the wiring in the peripheral region of the semiconductor wafer as a cause of a decrease in thickness of the wiring layer in the peripheral region, the peripheral region of the wafer tends to have the oxide film thereof etched, and thus tends to be reduced in thickness in device manufacturing. Thus, the semiconductor manufacturing process has factors in reducing the thickness of the wiring layer and the oxide film in the peripheral region of the wafer, so that the surface has a level difference.